From 4fdd08124c494660e8952b3fb75aa53258b94579 Mon Sep 17 00:00:00 2001
From: Ben Gainey <ben.gainey@arm.com>
Date: Mon, 5 Dec 2022 13:42:28 +0000
Subject: [PATCH] Fix incorrect handling of Cortex-X3 / Cortex-A715 /
 Neoverse-V2 cores due to missing profile match

---
 daemon/pmus.xml             | 6 +++---
 daemon/xml/PmuXMLParser.cpp | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/daemon/pmus.xml b/daemon/pmus.xml
index a3b5c162..d223f61b 100644
--- a/daemon/pmus.xml
+++ b/daemon/pmus.xml
@@ -92,7 +92,7 @@
     <pmu id="ARMv8_Neoverse_N1" cpuid="0x41d0c" core_name="Neoverse-N1" dt_name="arm,neoverse-n1" pmnc_counters="6" profile="8a" spe="arm_neoverse_n1_spe_pmu"/>
     <pmu id="ARMv8_Neoverse_N2" cpuid="0x41d49" core_name="Neoverse-N2" dt_name="arm,neoverse-n2" pmnc_counters="6" profile="8a" spe="arm_neoverse_n2_spe_pmu"/>
     <pmu id="ARMv8_Neoverse_V1" cpuid="0x41d40" core_name="Neoverse-V1" dt_name="arm,neoverse-v1" pmnc_counters="6" profile="8a" spe="arm_neoverse_v1_spe_pmu"/>
-    <pmu id="ARMv9_Neoverse_V2" cpuid="0x41d4f" core_name="Neoverse-V2" dt_name="arm,neoverse-v2" pmnc_counters="6" profile="9a" spe="arm_neoverse_v2_spe_pmu"/>
+    <pmu id="ARMv9_Neoverse_V2" cpuid="0x41d4f" core_name="Neoverse-V2" dt_name="arm,neoverse-v2" pmnc_counters="6" profile="8a" spe="arm_neoverse_v2_spe_pmu"/>
 
     <pmu id="ARMv8_Cortex_X1" cpuid="0x41d44" core_name="Cortex-X1" dt_name="arm,cortex-x1" pmnc_counters="6" profile="8a" spe="arm_cortex_x1_spe_pmu"/>
     <pmu id="ARMv8_Cortex_X1C" cpuid="0x41d4c" core_name="Cortex-X1C" dt_name="arm,cortex-x1c" pmnc_counters="6" profile="8a" counter_set="ARMv8_Cortex_X1" spe="arm_cortex_x1_spe_pmu"/>
@@ -101,8 +101,8 @@
     <pmu id="ARMv8_Cortex_A510" cpuid="0x41d46" core_name="Cortex-A510" dt_name="arm,cortex-a510" pmnc_counters="6" profile="8a"/>
     <pmu id="ARMv8_Cortex_A710" cpuid="0x41d47" core_name="Cortex-A710" dt_name="arm,cortex-a710" pmnc_counters="6" profile="8a"/>
 
-    <pmu id="ARMv9_Cortex_X3" cpuid="0x41d4e" core_name="Cortex-X3" dt_name="arm,cortex-x3" pmnc_counters="6" profile="9a"/>
-    <pmu id="ARMv9_Cortex_A715" cpuid="0x41d4d" core_name="Cortex-A715" dt_name="arm,cortex-a715" pmnc_counters="6" profile="9a"/>
+    <pmu id="ARMv9_Cortex_X3" cpuid="0x41d4e" core_name="Cortex-X3" dt_name="arm,cortex-x3" pmnc_counters="6" profile="8a"/>
+    <pmu id="ARMv9_Cortex_A715" cpuid="0x41d4d" core_name="Cortex-A715" dt_name="arm,cortex-a715" pmnc_counters="6" profile="8a"/>
 
     <!-- Arm China -->
     <pmu counter_set="DWT" id="ARMv8M_STAR" cpuid="0x63132" core_name="STAR" pmnc_counters="6" profile="8m"/>
diff --git a/daemon/xml/PmuXMLParser.cpp b/daemon/xml/PmuXMLParser.cpp
index 80125c6b..436ad9cf 100644
--- a/daemon/xml/PmuXMLParser.cpp
+++ b/daemon/xml/PmuXMLParser.cpp
@@ -284,7 +284,7 @@ bool parseXml(const char * const xml, PmuXML & pmuXml)
         //Check whether the pmu is v8, needed when hardware is 64 bit but kernel is 32 bit.
         bool isV8 = false;
         if (profileStr != nullptr) {
-            if (profileStr[0] == '8') {
+            if ((profileStr[0] == '8') || (profileStr[0] == '9')) {
                 isV8 = true;
             }
         }