Add IFU

Author: 0marAmr

instr_mem.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/07/2023 07:29:27 AM
+// Design Name: 
+// Module Name: instr_mem
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// Define the instruction memory module with three parameters:
+// - ADDRESS_WIDTH: the number of bits in the memory address
+// - INSTR_WIDTH: the number of bits in each instruction
+// - PROGRAM: the name of the file containing the program instructions
+module instr_mem
+    #(
+        parameter ADDRESS_WIDTH = 32,
+        parameter INSTR_WIDTH = 32,
+        parameter PROGRAM = "fibonacci.txt"
+    )
+    (
+        input wire [ADDRESS_WIDTH-1:0] addr, // Input address wire
+        output wire [INSTR_WIDTH-1:0] instr // Output instruction wire
+    );
+
+    localparam DEPTH = 64; // Set the depth of the instruction memory
+
+    // Declare a register array to hold the instruction memory contents
+    // The array is indexed by the address wire and holds instructions of width INSTR_WIDTH
+    reg [INSTR_WIDTH-1:0] memory [DEPTH-1:0];
+
+    // Initialize the instruction memory contents from the file specified by PROGRAM
+    initial begin
+        $readmemh(PROGRAM, memory);
+    end
+
+    // Assign the output instruction wire to the instruction memory contents at the input address
+    assign instr = memory[addr[31:2]]; // word aligned
+
+endmodule

instruction_fetch_unit.v

@@ -0,0 +1,89 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/07/2023 11:19:25 AM
+// Design Name: 
+// Module Name: instruction_fetch_unit
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+//  This is a module for the Instruction Fetch Unit (IFU)
+//  It retrieves the instruction from the memory and prepares it for execution
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module instruction_fetch_unit
+#(
+parameter ADDRESS_WIDTH = 32, // Defines the number of bits for the memory address
+parameter INSTR_WIDTH = 32, // Defines the number of bits for the instruction
+parameter PROGRAM = "fibonacci.txt", // The program file to be loaded into memory
+parameter N = 32 // Parameter defining the number of bits for the PC counter
+)(
+input wire clk, n_reset, // Clock and reset inputs
+input load, pc_src, // Load input for setting a new PC value
+input [1:0] imm_src, // immediate source
+output wire [INSTR_WIDTH-1:0] instr, // Output the fetched instruction
+output wire [INSTR_WIDTH-1:0] imm_ext
+);
+wire [N-1: 0] pc, pc_next, pc_plus_4, pc_target, imm_ext_internal;
+
+// Instantiate the program counter module
+prg_cntr #(.N(N)) program_counter (
+    .clk(clk),        // Clock input
+    .n_reset(n_reset),  // Reset input
+    .load(load),      // Load input
+    .pc_next(pc_next),  // Next PC output
+    .pc(pc)           // Current PC output
+);
+
+// Instantiate the instruction memory module
+instr_mem #(
+    .ADDRESS_WIDTH(ADDRESS_WIDTH), // Set the address width to 32 bits
+    .INSTR_WIDTH(INSTR_WIDTH),   // Set the instruction width to 32 bits
+    .PROGRAM(PROGRAM)           // Set the program file to PROGRAM
+) instruction_memory (
+    .addr(pc), // Address input wire
+    .instr(instr) // Fetched instruction output wire
+);
+
+// Calculate the PC+4 value
+addr #(.N(32)) pc_plus_4_addr (
+    .X(pc),
+    .Y(4),
+    .Z(pc_plus_4)
+);    
+
+// Sign-extend the immediate value for arithmetic operations
+sign_extend extended (
+    .instr_part(instr[31:7]), // Immediate value extracted from the instruction
+    .imm_src(imm_src),  // Source of the immediate value
+    .data_out_signed(imm_ext_internal)  // Sign-extended immediate value output
+);
+
+// Calculate the target PC for a branch or jump instruction
+addr #(.N(32)) pc_target_addr (
+    .X(pc),
+    .Y(imm_ext_internal),
+    .Z(pc_target)
+);
+
+// Select the next PC value based on the instruction type
+mux pc_next_mux (
+    .data_true(pc_target),  // Target PC
+    .data_false(pc_plus_4),  // PC+4
+    .sel(pc_src),  // Source of the next PC value
+    .data_out(pc_next)  // Next PC output
+);
+
+assign imm_ext = imm_ext_internal;
+
+endmodule

modules_testbenches/instr_mem_tb.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/07/2023 09:08:49 AM
+// Design Name: 
+// Module Name: instr_mem_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module instr_mem_tb;
+
+localparam ADDRESS_WIDTH = 32;
+localparam INSTR_WIDTH = 32;
+
+reg [ADDRESS_WIDTH-1:0] addr;
+wire [INSTR_WIDTH-1:0] instr;
+
+instr_mem dut (
+    .addr(addr),
+    .instr(instr)
+);
+
+task disp_instr(
+    input [ADDRESS_WIDTH-1:0] address
+);
+#10 $display("Instruction at address 0x%x is 0x%x", address, instr);
+endtask
+
+initial begin
+    // Load test program into memory
+    $readmemh("fibbonachi.txt", dut.memory);
+
+    // Test instruction memory reads
+        addr = 0;
+        disp_instr(addr);
+        addr = 4;
+        disp_instr(addr);
+        addr = 8;
+        disp_instr(addr);
+        addr = 12;
+        disp_instr(addr);
+        addr = 16;
+        disp_instr(addr);        
+        addr = 18;
+        disp_instr(addr);
+        addr = 20;
+        disp_instr(addr);
+        addr = 24;
+        disp_instr(addr);
+        $stop;
+end
+
+endmodule
+

modules_testbenches/instruction_fetch_unit_tb.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/07/2023 09:08:49 AM
+// Design Name: 
+// Module Name: instruction_fetch_unit_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+`timescale 1ns / 1ps
+
+module instruction_fetch_unit_tb;
+
+  // Parameters
+  parameter ADDRESS_WIDTH = 32;
+  parameter INSTR_WIDTH = 32;
+  parameter PROGRAM = "fibonacci.txt";
+  parameter N = 32;
+
+  // Inputs
+  reg clk;
+  reg n_reset;
+  reg load;
+  reg pc_src;
+  reg [1:0] imm_src;
+
+  // Outputs
+  wire [INSTR_WIDTH-1:0] instr;
+  wire [INSTR_WIDTH-1:0] imm_ext;
+
+  // Instantiate the module
+  instruction_fetch_unit #(
+    .ADDRESS_WIDTH(ADDRESS_WIDTH),
+    .INSTR_WIDTH(INSTR_WIDTH),
+    .PROGRAM(PROGRAM),
+    .N(N)
+  ) ifu (
+    .clk(clk),
+    .n_reset(n_reset),
+    .load(load),
+    .pc_src(pc_src),
+    .imm_src(imm_src),
+    .instr(instr),
+    .imm_ext(imm_ext)
+  );
+
+  // Clock generation
+  always #5 clk = ~clk;
+
+task initialize();
+begin
+    n_reset = 0;
+    clk = 0;
+    load = 1;
+    pc_src = 0;
+    imm_src = 0;
+    @(negedge clk);
+    n_reset = 1;
+end
+endtask
+
+task sequential_instruction();
+begin
+    pc_src = 0;
+    @(negedge clk);
+end
+endtask
+
+// Test sequence
+initial begin
+    initialize();
+    sequential_instruction();
+    sequential_instruction();
+    sequential_instruction();
+    sequential_instruction();
+
+    $stop;
+end
+
+endmodule
+

modules_testbenches/sign_extend_tb.v

@@ -0,0 +1,65 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/07/2023 01:13:02 AM
+// Design Name: 
+// Module Name: sign_extend_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+`timescale 1ns / 1ps
+
+module sign_extend_tb;
+
+    // Parameters
+    localparam INST_LEN = 32;
+
+    // Inputs
+    reg [31:7] instr_part;
+    reg [1:0] imm_src;
+    reg clk;
+
+    // Outputs
+    wire [INST_LEN-1:0] data_out_signed;
+    
+
+    // Instantiate the Unit Under Test (UUT)
+    sign_extend uut (
+        .instr_part(instr_part),
+        .imm_src(imm_src),
+        .data_out_signed(data_out_signed)
+    );
+
+    // Initialize Inputs
+    initial begin
+        instr_part = 32'h12345678;
+        imm_src = 2'b01; // s_type
+    end
+
+    // Stimulus
+    always #10 imm_src = (imm_src + 1) % 3;
+
+    // Print Output
+    always @(posedge clk) $display("data_out_signed = %h", data_out_signed);
+
+    // Clock
+    initial begin
+        clk =0;
+        forever #5 clk = ~clk;
+    end
+
+endmodule
+